1. Field of the Invention
The present invention relates to a method for converting an IBIS model to a SPICE behavioral model by extracting a resistor and a capacitor, and more particularly, to a method for converting an IBIS model to a SPICE behavioral model by extracting a resistor and a capacitor, for converting an Input/output Buffer Information Specification (IBIS) model provided as a behavioral model of an input/output pin of an integrated circuit, to a SPICE (Simulation Program with Integrated Circuit Emphasis) behavioral model.
2. Description of the Related Art
IBIS model refers to a digital input/output (I/O) model for fast signal integrity analysis of such as a transmission line effect, a crosstalk phenomenon, and a ringing phenomenon on printed circuit boards resulting from a high frequency signal as a clock speed of a digital integrated circuit is increased.
The IBIS model provides voltage-current (VI) and voltage-time (VT) information of a digital input/output pin in a format of table, and describes characteristics of a packaging parasitic component and an electrostatic discharge (ESD) prevention circuit. The IBIS behavioral model has a greater speed of simulation execution, owing to its VI and VT information provided in the format of table, than a SPICE model where a current value and a voltage value should be extracted at each node. The IBIS behavioral model is useful for a system level designer owing to its advantage of keeping a secret of an intellectual property (IP) of a circuit. However, it is required to convert the IBIS model to the SPICE behavioral model since the IBIS model has a limitation of various load simulation execution.
Then, a conventional technology for converting the IBIS model to the SPICE behavioral model will be described.
FIG. 1 is a flowchart illustrating a sequence of extracting a SPICE behavioral model from an IBIS model, for verification.
The IBIS model is largely divided into an input pin model and an output pin model. As shown in FIG. 1, an input pin SPICE model 105 can be simply provided using only DC VI table information 103 provided from the IBIS model 102, but an output pin SPICE model 106 needs a process of extracting a switching time coefficient 104 due to a switching characteristic. In this case, a VT table value 103 provided from the IBIS model 102 is used. The SPICE behavioral model generated from the IBIS model performs simulation 107 in the substantially same load condition as the SPICE model 101, and determines its simulation accuracy depending on whether two simulation results have a similar characteristic to any degree.
FIG. 2A illustrates the SPICE behavioral model of the IBIS model for an input pin. In the IBIS model, packaging components (C_pkg 201, L_pkg 202, and R_pkg 203) and a pad capacitor (C_comp 206) are provided as values, and a power clamp (POWER_clamp) and a ground clamp (GND_clamp) being ESD diodes 204 and 205 are provided as DC VI tables. The SPICE behavioral model of the IBIS model for the input pin is expressed as shown in FIG. 2B. The VI tables of the ESD diodes 204 and 205 are expressed as voltage controlled current sources (VCCS) 207 and 208 of the SPICE behavioral model.
The SPICE behavioral model of the IBIS model for an output pin is shown in FIG. 3. Packaging parasitic components (L_pkg 306, R_pkg 307, and C_pkg 308) and a pad capacitor (C_comp 305), and a power clamp (POWER_clamp) and a ground clamp (GND_clamp) being ESD diodes 303 and 304 are the same as those of the input model, and pull-up and pull-down transistors 301 and 302 are additionally provided. The IBIS model includes VI tables 310, 311 and 312 being static characteristics of the pull-up and pull-down transistors 301 and 302; and a VT table 313 being a dynamic characteristic. Reference numerals 314 and 315 denote a fixture resistance (R_fix) and a fixture voltage (V_fix), respectively.
In order to embody an accurate output SPICE behavioral model, an accurate model of a switching component is required. A conventional technology adopts a method for obtaining a switching time coefficient using a circuit equation, as a switching component modeling method. According to this method, the SPICE behavioral model of the output pin is expressed as in FIG. 3C. The pull-up transistor is expressed by a multiplication 320 of a switching time coefficient (Ku(t)) and a static current (Ipu(V)), and the pull-down transistor is expressed by a multiplication 321 of a switching time coefficient (Kd(t)) and a static current (Ipd(V)). Reference numerals 322 and 323 denote DC VI tables of the diodes 303 and 304. Accordingly, a total transition current Iout(t) is expressed as follows:Iout(t)=Kux(t)×Ipu(Vdie)+Kdx(t)×Ipd(Vdie)+Ipc(Vdie)+Igc(Vdie)  [Equation 1]
FIG. 3B illustrates an IBIS VT table measurement circuit. A transition current Iout(t) is expressed by the circuit equation as in the following Equation 2:
                                          I            out                    ⁡                      (            t            )                          =                  -                      (                                                            C                  comp                                ⁢                                  ⅆ                                      ⅆ                    t                                                  ⁢                                                      V                    die                                    ⁡                                      (                    t                    )                                                              +                                                                                          V                      die                                        ⁡                                          (                      t                      )                                                        -                                      V                    fix                                                                    R                  fix                                                      )                                              [                  Equation          ⁢                                          ⁢          2                ]            
The switching time coefficients Ku(t) and Kd(t) are obtained by combining the Equations 1 and 2.
The above conventional technology requires two pieces of VT table information in order to obtain two switching time coefficients, and has a drawback of inaccuracy of the SPICE model including the time information in FIG. 3C. That is, the conventional art has a limitation of being capable of extraction only in an environment where two or more VT tables are given in an IBIS version 2. 1 or above.